1. 1. S Rajesh and M R Sanjay Kumar “Generation of radar waveform based on DDS using FPGA and DAC” international journal of advanced research in electronics and instrumentation engineering,vol.4 issue 5 may 2015.
   2. Ms.Khushboo D.Babhulkar and Mrs. Pradnya J.S “Design of multi-functional high frequency DDS using HDL for soft IP core”ICIAC 12-13th April 2014.
   3. Design and implementation of low-pass,high-pass and band-pass finite impulse response (FIR) filter using FPGA.Scientific research publication.
   4. Ketan Mishra and Soheb Munir “Design and VHDL implementation of UART with error status register” international journal of advance research in computer science and software engineering 2014.
   5. Suvadip Roy, L. Srivani, D. Thirugnana Murthy “Digital Filter Design Using FPGA” International Journal Of Engineering And Innovative Technology (IJEIT) Volume 5, Issue 4, October 2015.
   6. Apurva Singh Chauhan, Vipul Soni “Design Of FIR Filter On Fpgas Using IP Cores” International Journal Of Advancements In Technology
   7. Jadhav Nitish Anandrao” Ip Core Generation Of Direct Digital Synthesizer” International Journal Of Innovative Technologies, VOL. 01, ISSUE 01, AUG 2013
   8. Abhinav V. Deshpande “ Design Of Synthesizable IP Core Using DDS For VHDL” Research Article Volume 6 Issue No. 8.
   9.  Xilinx, Inc.,“DSP Design Flows In FPGA Tutorialslides”. San Jose, California, USA, Pp. 1-82, 2003.
   10.  Spartan-3 Starter Kit Board User Guide UG130 (V1.1) May 13, 2005