[1] Himanshu Thapliyal, Saurabh Kotiyal* and M.B Srinivas, Design and Analysis of A Novel Parallel Square and Cube Architecture Based On Ancient Indian Vedic Mathematics.

[2] Design Of A High Speed 8x8 Ut Multiplier Using Reversible Logic Gates Sadhu Suneel1, L.M.L.Narayana Reddy M. Tech student , Assistant professor in ECE department.

 [3] S. Deepak and Binsu J Kailath, 2012, Optimized MAC unit design, (2012) IEEE EDSSC 2012, IEEE International Conference on Electron Devices and Solid-State Circuits held from 3-5 Dec. 2012.

[4] Prabir Saha, Arindam Banerjee, Partha Bhattacharyya , Anup Dandapat, 2011. High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics, IEEE Students’ Technology Symposium, IIT Kharagpur.

[5] Ramachandran.S, Kirti.S.Pande, Design, Implementation and Performance Analysis of an Integrated Vedic Multiplier Architecture, International Journal Of Computational Engineering Research, May-June 2012, Vol. 2. Issue No.3, 697- 703.

[6] Pavan Kumar U.C.S, Saiprasad Goud A, A.Radhika, FPGA Implementation of High Speed 8- bit Vedic Multiplier Using Barrel Shifter, International Journal of Emerging Technology and Advanced Engineering, Volume 3, Issue 3, March 2013

[7] Honey Durga Tiwari, Ganzorig Gankhuyag, Chan Mo Kim, Yong Beom Cho, Multiplier design based on ancient Indian Vedic Mathematics, 2008 IEEE International SOC Design Conference.

[8] Vinay Kumar, 2009 Analysis, Verification and FPGA Implementation Of Vedic Multiplier With Bist Capability, Thapar University.