Author : Aditi Singh 1
Date of Publication :17th August 2017
Abstract: Continuous time ∑∆ Convertor is an highly power efficient modulator which has overcome the pipeline and Discrete time modulator as they require more number of high speed gain stages.Morever it is has an aliasing free Nquist band which is made available by oversampling and an on chip filter is also present.The input is resistive with no sampling so it is easier to drive the entire modulator with miniscule noise and an on- chip clock conditioner is used.There are several drawbacks associated with CTDSM like clock jitter and excess loop delay.In this paper different techniques to reduce Excess Loop Delay(ELD) in a continuous time delta sigma modulator is analysed and presented.
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