Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Power Reduction Testing Techniques of BIST, LFSR & ATPG for Low Power Circuits

Author : P. Ramesh 1 Dr. D.N Rao 2 Dr. K. Srinivasa Rao 3

Date of Publication :30th November 2017

Abstract: The power techniques that reduce power consumption during test application are generally referred to as power- conscious testing, power-aware testing, power-constrained testing, or low-power testing. These terms will be interchanged for use throughout the chapter whenever fit. Built-in-Self-Test (BIST) is becoming an alternative solution to the rising costs of external electrical testing and increasing complexity of devices Small increase in the cost of the system reduces large testing cost. BIST is a design technique that allows a circuit to test itself Test pattern generator (TPG) using Linear Feedback Shift Register (LFSR) is proposed which is more suitable for BIST architecture. We have implemented Universal asynchronous receiver transmitter (UART) with BIST capability using different LFSR techniques and compared these techniques for the logic utilization in SPARTAN3 XC3S200-4FT256 FPGA device.

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