International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume5,February 2018,

Topic : A Fault-Tolerant Memory System for Nano-Memory Applications

Authors:Pradeep Kalakoti || Kalakoti. Kalyan

Abstract:Due to the increase in the soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as well and must also be protected. We introduce a new approach to design fault-secure encoder and decoder circuitry for memory designs. Hamming codes are often used in today’s memory systems to correct a single error and detect double errors in any memory word. In these memory architectures, only errors in the memory words are tolerated and there is no preparation to tolerate errors in the supporting logic (i.e. encoder and corrector). However combinational logic has already started showing susceptibility to soft errors, and therefore the encoder and decoder (corrector) units will no longer be immune from the transient faults. Therefore, protecting the memory system support logic implementation is more important. Here we proposed a fault tolerant memory system that tolerates multiple errors in each memory word as well as multiple errors in the encoder and corrector units. We illustrate using Euclidean Geometry codes and Projective Geometry codes to design the fault-tolerant memory system, due to their well-suited characteristics for this application..

Keywords: Soft error rate, Fault-secure, Euclidean Geometry Code.

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DOI: 01.1617/vol5/iss2/pid84652


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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