Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Implementation of Area and Memory Efficient Combined ByteSub and InvByteSub Transformation for AES Algorithm

Author : Sushma D K 1 Dr. Manju Devi 2

Date of Publication :25th May 2018

Abstract: Efficient implementation of combined ByteSub and InvByteSub transformation for encryption and decryption in advanced encryption standard (AES) architecture using the composite field arithmetic in finite fields GF (256) or GF (28) hence this approach is more advantages than the conventional LUT method that incurs the unbreakable delay, greater amount of memory and area. The proposed architecture which is combined implementing of S-box and InvS-box makes use of an enable pin to perform encryption and decryption in AES. The architecture uses combinational logic, as both S-box and InvS-box are implemented on same hardware reduces the area and gate count by the large amount. Low power consumption due to resource sharing by the multiplicative inverse module of the proposed system. The proposed architecture is accouterment on Spatan6 board using Verilog HDL in Xilinx ISE 14.6.

Reference :

    1. Edwin NC Mui, "Practical Implementation of Rijndael SBox Using combinational Logic", Custom R&D Engineer Texco Enterprise
    2. Xinmiao Zhang and Keshab K. Parhi, “High-Speed VLSI Architectures for the AES Algorithm.”, IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol.12, No. 9, September 2004.
    3. P.V.S.ShastI, Anuja Agnihotri, Divya Kachhwaha, Jayasmita Singh and Dr.M.S.Sutaone, “A Combinational Logic implementation of S-box of AES”, 54th International Midwest Symposium on Circuit and Systems, 2011
    4. Bhoopal Rao Gangadari and Shaik Rafi Ahamed, “FPGA Implementation of Compact S-Box for AES algorithm using Composite field arithmetic”.
    5. Vincent Rijmen, “Efficient Implementation of the Rijndael S-Box.”, Katholieke Universities Leuven, Dept. ESAT. Belgium.
    6. Akashi Satoh, Sumio Morioka, Kohji Takano and Seiji Munetoh, “A Compact Rijndael Hardware Architecture with S-Box Optimization.” Springer-Verilog Berlin Heidelberg, 2001.
    7. S.SrideviSathya Priya, N.M.SivaMangai “Multiplexer based High Throughput S-box for AES Application” Karunya University, ICECS 2015
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