International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume5,June 2018,

Topic : A 12nm FinFET Level Shifter for near threshold circuits

Authors:Radhika || Jayadeva T S

Abstract:Power has turned into the essential plan imperative for chip designers today. While Moore's law perpetuates to provide additional transistors, power related constraints have started to preclude those devices from being utilized. These days, low power designs, particularly multi-voltage designs turn into a well-known and proficient approach to reduce both dynamic power and static power consumption. A key parameter in designing of effective multiple supply circuits is limiting the cost of the level transformation between diverse voltage domains while keeping up the overall robustness of the design. To such a reason, level shifter (LS) circuits can be used. In order to achieve reduction in power consumption, a proposed level shifter topology has been used in this paper which uses a low contention between PMOS and NMOS transistor due to which dynamic energy consumption is reduces, speed is also increased due to the use of a feedback loop and also due to the near-threshold computing its energy efficiency is more. As 12nm technology node delivers better density and a performance boost over Global Foundries' current-generation 14nm FinFET, which satisfies the processing needs of the most demanding compute-intensive applications from artificial intelligence and virtual reality to high-end smart-phones and networking infrastructure, the proposed level shifter has been scaled down to 12nm technology node which is capable of converting near-threshold voltage signal to above threshold voltage signal(i.e. from 250mV to 500mV) with 284.1229nW of power dissipation.

Keywords: FinFET's, level shifter, low power, near threshold

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DOI: 01.1617/vol5/iss6/pid51789


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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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