Date of Publication :30th September 2020
Abstract: The paper present the design of hybrid FIR filter architecture for various filter applications. The combination of ripple carry adder, carry look-ahead adder and carry select adders is used for the designing of the core circuit components. The speed of the operation in the circuit is increased by the parallel generation of the carry by look ahead carry generation blocks and is propagated using modified carry skip adders. The radix-4 booth multiplier, which has a low-power-delay-product, is used as the multiplier in the design of the filter. The normal ripple carry adder in the booth multiplier is replaced by the modified hybrid adder for increasing the speed and performance of the multiplier unit. Thus the speed of the designed filter can be increased by the use of modified booth multiplier and lowers the propagation delay. The design and implementation is done using the cadence RTL compiler with gpdk of 45 nm technology.
Reference :
-
- Anubhuti Mittal,Ashutosh Nandi, Disha Yadav.: Comparative study of 16-order FIR filter design using different multiplication Techniques. IET Circuits, Devices & Systems Volume: 11 , Issue: 3 , 5 2017.
- M. Alioto, and G. Palumbo.: A simple strategy for optimized design of one-level carry-skip adders. IEEE Trans. Circuits Syst. I, Fundamental Theory Appl., Vol. 50, no. 1, pp. 141–8, Jan. 2003.
- O. J. Bedrij.:Carry-select adder. IRE Trans. Electron. Comput., Vol. EC-11, no. 3, pp. 340–6, 1962.
- B. K.Mohanty, and S.Kumar.:Patel area–delay– power efficient carry-select adder. IEEE Trans. Circuits Syst.-II: Exp. Briefs, Vol. 61, no. 6, pp. 418–22, 2014.
- B. Ramkumar, and H. M. Kittur.:Low-power and area efficient carry-select adder. IEEE Trans. Very Large Scale Integ. Syst., Vol. 20, no. 2, pp. 371–5, 2012.
- T. Y. Chang, and M. J.Hsiao.:Carry-select adder using single ripple carry adder. Electron. Lett. Vol. 34, no. 22, pp. 2101–3, 1998.
- Y. Kim, and L. S. Kim.: 64-bit carry-select adder with reduced area. Electron
- P. Pramod & T. K. Shahana.: Delay and Energy Efficient Modular Hybrid Adder for Signal Processor Architectures. IETE Journal of Research,2019
- Kazi Nikhat Parvin and Md.Zakir Hussain.: Multiplication Techniques for an Efficient FIR Filter Design for Hearing aid Applications. ICISC 2018
- S. Thakral, D. Goswami, R. Sharma, C. K. Prasanna, A.Mahesh, and A. M. Joshi. :Design and implementation of a high speed digital FIR filter using unfolding, in Proceedings of 7th IEEE Power India International Conference, Bikaner, India, 2016.
- H.Xue, R.Patel, N.V.V.K.Boppana, S.Ren.: Low- power-delay product radix-4 8*8 booth multiplier in CMOS. Electronic letters, 54(6) (2018) 344-46.
- M. D. Ercegovac, and T. Lang. Digital Arithmetic. San Mateo, CA.: Mogan Kaufmann, 2004.J. M. Rabaey, A. Chandrakasa, and B. Nikolic. Digital Integrated Circuits. A Design Perspective. 2nd ed. Englewood Cliffs, NJ, USA: Prentice-Hall, 2003.
- S. Ghosh, D. Mohapatra, G. Karakonstantis, and K. Roy.: Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking. IEEE Trans. Very Large Scale Integr. Syst., Vol. 18, no. 9, pp. 1301–9, Sep. 2010.
- R. W. Doran, “Variants of an improved carry look-ahead adder.:IEEE Trans. Comp., Vol. 37, no. 9, pp. 1110–3, 1988
- M. Alioto, and G. Palumbo.: A simple strategy for optimized design of one-level carry-skip adders. IEEE Trans. Circuits Syst. I, Fundamental Theory Appl., Vol. 50, no. 1, pp. 141–8, Jan. 2003.
- R. P. Brent, and H. T. Kung.: A regular layout for parallel adders. IEEE Trans. Comp., Vol. C-31, no. 3, pp. 260–4, 1982.. Lett., Vol. 37, no. 10, pp. 614–5, 2001.
- M. Bahadori, M. Kamal, and A. Afzali-Kusha.: High-speed and energy-efficient carry skip
- adder operating under a wide range of supply voltage levels. IEEE Trans.Very Large Scale Integ. Syst., Vol. 24, no. 2, pp. 421–433, Feb. 2016.
- T. Han, and D. A. Carlson.: Fast area-efficient VLSI adders, in Proceedings of the 8th IEEE Symposium on Computer Arithmetic, Como, Italy, May 1987, pp. 49– 56
- S. K. Mathew.: A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder core, in Symposium on VLSI Circuits Digest of Technical Papers. Hillsboro, USA: Circuits Research, Intel Labs, Intel Corporation, 2002, pp. 126–7.
- H.Q.Dao, B.R.Zeydel and V.G.Oklobdzija.: Energy optimization of pipelined digital systems using circuit sizing and supply scaling. IEEE Trans. VLSI Syst., Vol. 14, no. 2, pp. 122–34, 2006
- Y. He and C.-H. Chang.: A power-delay efficient hybrid carry look ahead/carry-select based redundant binary to two’s complement converter. IEEE Trans. Circuits Syst.-I Reg. Pap., Vol. 55, no. 1, pp. 336– 46, Feb. 2008
- K. Chirca, M. Schulte, J. Glossner, H. Wang, B. Mamidi, P. Balzola, and S. Vassiliadis.: A static low-power, high- performance 32-bit carry skip adder,in Proceedings of Euro micro Symposium on Digital System Design (DSD), Rennes, France, Aug. 31–Sep. 3, 2004, pp. 615–
- Cadence 45 nm, 90 nm and 180 nm gpdk standard cell libraries. Available: https://support.cadence.com/.