International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume4,March 2017,

Topic : Convolution and Stochastic Pooling Algorithm

Authors:Monish Katari || Reethu Gali Ramesh, MSA Srivatsava

Abstract:This paper presents an efficient hardware implementation of Convolution and Stochastic pooling algorithm. The main objective of the design is to minimize the area and power, while maximizing the throughput. Performing Convolution and Stochastic pooling in CPU consumes high amount of power and low performance relative to hardware accelerator implementation. In this paper, we propose a hardware accelerator to minimize area, power and maximize throughput. We also propose architectural techniques like Interleaving and folding to improve power and area. The optimized approach which is mapped to a 28nm ASIC target demonstrated significant power and area reduction when compared to traditional model. On the other hand, the optimized approach mapped to a FPGA target has increased source utilization when compared to conventional model..

Keywords: Convolutional Neural Network (CNN), Central processing unit (CPU), Graphics processing unit (GPU)

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DOI: 01.1617/vol4iss3pid007


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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IMPACT FACTOR: 3.689

ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
ORCiD Research ID : 0000-0001-9540-6799

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Journal Code : IJERECE
Electronic ISSN : 2394-6849
Impact Factor : 3.689
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