Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Reduction of Current Leakage in VLSI Systems

Author : Tayab Mustaq Ahmed 1 Deepak H.A 2

Date of Publication :7th March 2017

Abstract: This paper consisting of the general information about the VLSI followed by the history and development of the VLSI. MOORE's LAW is explained shortly and the designing of the VLSI circuits is explained by the design of VLSI by HIERARCHYSTRUCTURE. In this paper some of the general discussion on the current leakage reduction in the processors are discussed in which the reduction of current leakage by using switches are included and also we can reduce the current leakage in the circuit by using "sleep transistor". Sleep transistors are the transistor which turns off completely when the circuit is not in use. And we have also discussed some of the aspects related to reduction of current leakage in VLSI using simple NAND gate we have shown both types using MOSFET transistor and also by using simple Transistors. We have designed a NAND gate using transistor BC547 so that it will be easy to understand and to convey information or technique in much more easier way. In the end we concluded that using of sleep circuit(sleep transistor) is very effective technique. After this we have also discussed some the major issue or the problem faced while designing our circuit which is also important because we need to know the limitations before designing any circuit.

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