Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

High-Speed, Low Area and Energy Efficient 32bit Carry Skip Adder using verilog HDL

Author : Konduru Lakshmi 1 Bhanu Prakash Reddy 2 Dr.S.Vijaya Kumar 3

Date of Publication :7th March 2017

Abstract: Adders are basic essential component used in DSPs Processors and Digital filters and widely used in the Digital Integrated Circuits and also in Analog ICs.In this paper, a carry skip adder structure that has a higher speed, Low area as well as lower energy consumption compared with other adders is presented. The speed and reduction in the design area can be achieved by using “HYBRID MUX” instead of conventional MUX for skip logic in the existing method. In addition, instead of utilizing compound gates (AOI&OAI), the proposed structure makes use of “HYBRID MUX” for the skip logic. The Proposed structure assessed by comparing their speed, delay, area & energy parameters with those of other adders using a 45-nm static CMOS technology. The results that are obtained by Xilinx tool. Simulation reveals, on average 45% and 40% improvements in the delay &energy, respectively compared with conventional one. The power delay product is the lowest among all adders.

Reference :

  1. [1] I. Koren, Computer Arithmetic Algorithms, 2nd ed. Natick, MA, USA: A K Peters, Ltd., 2002.

    [2] R. Zlatanovici, S. Kao, and B. Nikolic, ―Energy– delay optimization of 64-bit carry-lookahead adders with a 240 ps 90 nm CMOS design example,‖ IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 569–583, Feb. 2009.

    [3] S. K. Mathew, M. A. Anders, B. Bloechel, T. Nguyen, R. K. Krishnamurthy, and S. Borkar, ―A 4- GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS,‖ IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 44–51, Jan. 2005..

    [4] V. G. Oklobdzija, B. R. Zeydel, H. Q. Dao, S. Mathew, and R. Krishnamurthy, ―Comparison of highperformance VLSI adders in the energy-delay space,‖ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 754–758, Jun. 2005.

    [5] B. Ramkumar and H. M. Kittur, ―Low-power and areaefficient carry select adder,‖ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2, pp. 371–375, Feb. 2012.

    [6] M. Vratonjic, B. R. Zeydel, and V. G. Oklobdzija, ―Lowand ultra low-power arithmetic units: Design and comparison,‖ in Proc. IEEE Int. Conf. Comput. Design, VLSI Comput. Process. (ICCD), Oct. 2005, pp. 249–252.

    [7] C. Nagendra, M. J. Irwin, and R. M. Owens, ―Area-timepower tradeoffs in parallel adders,‖ IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 43, no. 10, pp. 689–702, Oct. 1996.

    [8] Y. He and C.-H. Chang, ―A power-delay efficient hybrid carry- lookahead/carry-select based redundant binary to two’s complement converter,‖ IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 1, pp. 336–346, Feb. 2008.

    [9] C.-H. Chang, J. Gu, and M. Zhang, ―A review of 0.18 μm full adder performances for tree structured arithmetic circuits,‖ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 686–695, Jun. 2005.

    [10] D. Markovic, C. C. Wang, L. P. Alarcon, T.-T. Liu, and J. M. Rabaey, ―Ultralow-power design in near-threshold region,‖ Proc. IEEE, vol. 98,no. 2, pp. 237–252, Feb. 2010.

    [11] R. G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge, ―Near-threshold computing: Reclaiming Moore’s law through energy efficient integrated circuits,‖ Proc. IEEE, vol. 98, no. 2, pp. 253–266, Feb. 2010.

    [12] S. Jain et al., ―A 280 mV-to-1.2 V wide-operatingrange IA-32 processor in 32 nm CMOS,‖ in IEEE Int. SolidState Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2012, pp. 66–68.

    [13] R. Zimmermann, ―Binary adder architectures for cellbased VLSI and their synthesis,‖ Ph.D. dissertation, Dept. Inf. Technol. Elect. Eng., Swiss Federal Inst. Technol. (ETH), Zürich, Switzerland, 1998.

    [14] D. Harris, ―A taxonomy of parallel prefix networks,‖ in Proc. IEEE Conf. Rec. 37th Asilomar Conf. Signals, Syst., Comput., vol. 2. Nov. 2003, pp. 2213–2217.

    [15] P. M. Kogge and H. S. Stone, ―A parallel algorithm for the efficient solution of a general class of recurrence equations,‖ IEEE Trans. Comput., vol. C-22, no. 8, pp. 786– 793, Aug. 1973.

    [16] V. G. Oklobdzija, B. R. Zeydel, H. Dao, S. Mathew, and R. Krishnamurthy, ―Energy-delay estimation technique for high- performance microprocessor VLSI adders,‖ in Proc. 16th IEEE Symp. Comput. Arithmetic, Jun. 2003, pp. 272–279.

    [17] M. Lehman and N. Burla, ―Skip techniques for highspeed carry- propagation in binary arithmetic units,‖ IRE Trans. Electron. Comput., vol. EC-10, no. 4, pp. 691–698, Dec. 1961.

    [18] K. Chirca et al., ―A static low-power, high-performance 32-bit carry skip adder,‖ in Proc. Euromicro Symp. Digit. Syst. Design (DSD), Aug./Sep. 2004, pp. 615–619.

    [19] M. Alioto and G. Palumbo, ―A simple strategy for optimized design of one-level carry-skip adders,‖ IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 1, pp. 141–148, Jan. 2003.

    [20] S. Majerski, ―On determination of optimal distributions of carry skips in adders,‖ IEEE Trans. Electron. Comput., vol. EC-16, no. 1, pp. 45–58, Feb. 1967.

    [21] A. Guyot, B. Hochet, and J.-M. Muller, ―A way to build efficient carry- skip adders,‖ IEEE Trans. Comput., vol. C36, no. 10, pp. 1144–1152, Oct. 1987.

    [22] S. Turrini, ―Optimal group distribution in carry-skip adders,‖ in Proc. 9th IEEE Symp. Comput. Arithmetic, Sep. 1989, pp. 96–103.

    [23] P. K. Chan, M. D. F. Schlag, C. D. Thomborson, and V. G. Oklobdzija, ―Delay optimization of carry-skip adders and block carry-lookahead adders using multidimensional dynamic programming,‖ IEEE Trans. Comput., vol. 41, no. 8, pp. 920–930, Aug. 1992.

    [24] V. Kantabutra, ―Designing optimum one-level carryskip adders,‖ IEEE Trans. Comput., vol. 42, no. 6, pp. 759– 764, Jun. 1993.

    [25] V. Kantabutra, ―Accelerated two-level carry-skip adders—A type of very fast adders,‖ IEEE Trans. Comput., vol. 42, no. 11, pp. 1389–1393, Nov. 1993.

    [26] S. Jia et al., ―Static CMOS implementation of logarithmic skip adder,‖ in Proc. IEEE Conf. Electron Devices Solid-State Circuits, Dec. 2003, pp. 509–512. [27] H. Suzuki, W. Jeong, and K. Roy, ―Low power adder with adaptive supply voltage,‖ in Proc. 21st Int. Conf. Comput. Design, Oct. 2003, pp.

    [28] H. Suzuki, W. Jeong, and K. Roy, ―Low-power carryselect adder using adaptive supply voltage based on input vector patterns,‖ in Proc. Int. Symp. Low Power Electron. Design (ISLPED), Aug. 2004, pp. 313–318.

    [29] Y. Chen, H. Li, K. Roy, and C.-K. Koh, ―Cascaded carry-select adder (C2 SA): A new structure for low-power CSA design,‖ in Proc. Int. Symp. Low Power Electron. Design (ISLPED), Aug. 2005, pp. 115–118.

    [30] Y. Chen, H. Li, J. Li, and C.-K. Koh, ―Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI,‖ in Proc. ACM/IEEE Int. Symp. Low Power Electron. Design (ISLPED), Aug. 2007, pp. 195–200.


Recent Article