1. Athira P.K. and Mahalakshmi M. (2014) „Low Power Design of Dual Mode Logic using Stacking Power Gating‟, International Journal of Review in Electronics & Communication Engineering, Vol. 2, No.

2, pp. 63- 67. 2. Kaizerman A., Fisher S. and Fish A. (2013) „Subthreshold Dual Mode Logic‟, IEEE transaction on VLSI systems, Vol. 21, No. 5, pp.979-983.

3. Kumar M., Hussain A.Md. and Paul S.K. (2013) „New Hybrid Digital Circuit Design Techniques for Reducing Subthreshold Leakage Power in Standby Mode‟, Circuits and Systems, Vol. 4, No. 1, pp.75-82.

4. Lakshmisree P. V. and Raghu M.C. (2014) „Design of Subthreshold Logic Gates with Power Gating Techniques‟, International Journal of Research in Engineering and Technology, Vol. 3, No. 4, pp. 174- 180.

5. Levi I., Belenky A. and Fish A. (2014) „;Logical Effort for CMOS Based Dual Mode Logic Gates‟, IEEE transaction on VLSI Systems, Vol. 22, No. 5, pp. 1042- 1053.

6. Nigam K.K. and Tiwari A. (2012) „Zigzag Keeper: A New Approach for Low Power CMOS Circuit‟, International Journal of Advanced Research in Computer and Communication Engineering, Vol. 1, No. 9, pp. 694-699.

7. Reddy A.K. and Kumar S. (2013) „A Novel Technique for Ground Bounce Noise Reduction in Deep Sub Micron Circuits‟, International Journal of Innovative Technology and Research, Vol. 1, No. 5, pp.485-490.