International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume2,March 2015,

Topic : High Efficiency Low Complexity Chase Architecture for Reed-Solomon Decoder of RS(255,K)

Authors:Remalli Dinesh || Sandeep Bansal,Damandeep Singh, Shaik Shabeena

Abstract:In contrast to all existing ASD soft-decision decoding concepts for RS codes, only low-complexity chase algorithm can attain improved tradeoff in performance-complexity with significant coding gain on HDD with polynomial complexity. LCC decoding scheme utilized 2 ? test vectors having less computational complexity in addition to enhanced coding gain. Instead of short RS codes, LCC decoding is required to interpolate bulk of test vectors which results in long latency. Therefore, interpolations as well as polynomial selection are hefty part of LCC decoder with long RS code and significant value of ?. Besides, innovative designs being developed to alter the interpolation and polynomial complexity for the efficient recovery of the codeword for the given test vectors in LCC decoding. So, toward the codeword recovery for an RS (n, k) code erasure decoding, Neilson algorithm, coordinate transformation etc. being applied on the RS code segment. Also Chine search method can be applied over the interpolation output and it can be realized through constant multipliers which save the cost factor. For the selected 8 test vectors applied on RS (255, k) efficiency can be lead up to very high with power reduction for GF (210)..

Keywords: CMOS, LCC, Low power, Interpolation, Polynomial evaluation, Reed-Solomon, Soft-decision.

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DOI: 01.1617/vol2iss3pid023


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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