Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Design of 512-bit Wallace Tree Multiplier by Sklansky Adder

Author : S.M.Dinesh 1 T.S.Athira 2 Y.Hariesh 3

Date of Publication :7th April 2016

Abstract: Power consumption has become a crucial concern in today’s VLSI system style. The growing marketplace for quickfloating purpose coprocessors, digital signal process chips, and graphics processor has created a requirement for topspeed and space economical multipliers. A Wallace tree multiplier factor may be a improved version tree based mostly multiplier factor design. It uses carry save addition rule to cut back the latency. This paper aims at extrareduction of latency and power consumption of the Wallace tree multiplier factor. The simulation has been meted outmistreatment the Xilinx ISE tool.

Reference :

  1. [1] A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design. Norwell. MA:Kluwer.

    [2] C. H. Chang, J. Gu, M. Zhang, “Ultra low-voltage low power CMOS 4-2 and 5-2 compressorsfor fast arithmetic circuits” IEEE Transactions on Circuits and Systems .

    [3] H. Neil. Weste and Kamran Eshraghian, “Principles of CMOS VLSI design-A Systems Perspective,” Pearson Edition Pvt Ltd. 3rd edition, 2005

    [4] List I. Abdellatif, E. Mohamed, “Low-Power Digital VLSI Design, Circuits and Systems,” Kluwer Academic Publishers, 1995.

    [5] H. Neil. Weste and Kamran Eshraghian, “Principles of CMOS VLSIdesign-A Systems Perspective,” Pearson Edition Pvt Ltd. 3rd edition, 2005


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