Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Reference :

  1. [1] Chi-Heng,Yi-Min Lin,Hsia-Chia Chang and Chen-Yi Lee,“An MPCN Based BCH Codec ArchitectureWith Arbitrary Error Correcting Capability”, IEEE TrancationsOn Very Large Scale Integration Systems.VOL.23,NO.7,JULY 2015.

    [2] K. Lee, S. Lim, and J. Kim,“Low-cost, low-power and high-throughput BCH decoder for NAND flash memory,”, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS),May 2012, pp. 413415.

    [3] Y. Cai, E. F. Haratsch, O. Mutlu, and K. Mai, “Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis”, in Proc. Design, Autom.Test Eur. Conf. Exhibit. (DATE), Mar. 2012,pp. 521526.

    [4] W. Liu, J. Rho, and W. Sung,“Low-power highthroughput BCH error correction VLSI design for multilevel cell NAND flash memories, ”, in Proc. IEEE Workshop Signal Process. Syst. Design Implement., Oct. 2006, pp. 303308.

    [5] T.-H. Chen, Y.-Y. Hsiao, Y.-T. Hsing, and C.- W.Wu,“An adaptive-rate error correction scheme for NAND flash memory”, in Proc. 27th IEEE VLSI Test Symp. (VTS),May 2009, pp. 5358.

    [6] S. Li and T. Zhang,“Improving multi-level NAND flash memory storage reliability using concatenated BCHTCM coding,”, IEEE Trans.Very Large Scale Integr.(VLSI) Syst., vol. 18, no. 10, pp. 14121420,Oct. 2010.

    [7] S. Tanakamaru, C. Hung, and K. Takeuchi,“Highly reliable and low power SSD using asymmetric coding and stripe bitline-pattern elimination programming, ”, IEEEJ. Solid-State Circuits, vol. 47, no. 1, pp. 8596, Jan. 2012.

    [8] Y.Lee, H. Yoo, I. Yoo, and I.-C. Park,“6.4 Gb/s multithreaded BCH encoder and decoder for multi- R. Cherukuri, “Agile encoder architectures for strengthadaptive long BCH codes”,in Proc. IEEE GLOBECOM Workshops, Dec. 2010,pp. 19001904.

    [9] Y.M. Lin, C.-H. Yang, C.-H. Hsu, H.-C. Chang, and C.-Y. Lee “A MPCN-based parallel architecture in BCH decoders for NAND flash memory devices”, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58,no. 10, pp. 682686, Oct. 2011.

    [10] G. Fettweis and M. Hassner, “A combined ReedSolomon encoder and syndrome generator with small hardware complexity”, in Proc. IEEE Int. Symp. Circuits Syst.(ISCAS), vol. 4. May 1992, pp. 18711874.


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