Author : Rinu Susan Babu 1
Date of Publication :7th April 2016
Abstract: In fixed point number representation, digits after the decimal point is fixed and it does not provide a high precision value, while in floating point representation the decimal point is not fixed. Based on the concept of floating point number a fused floating point arithmetic unit is designed. Generally alignment, normalization and rounding are the complex process required in floatingpoint operation, which significantly increase the latency. This work relies on a fused floating-point three-term arithmetic unit, which includes a fused floating point three term adder unit, a fused floating point three term subtractor unit and a fused floating point three term multiplier unit. Here addition is the basic operation used in adder unit, subtractor unit and multipliers unit, which results in decrease or increase of delay. In order to improve the performance of a three term floating point arithmetic unit, carry save adder is replaced by a parallel prefix adder like kogge stone adder. A parallel prefix addition mainly includes a pre-processing stage, a carry generation stage and a post processing stage. This floating point three term arithmetic unit using parallel prefix adder is designed using VHDL language and it is synthesised in Xilinx ISE Design Suit 13.2 and can be simulated in Model SimSE 6.3f.
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