International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume3,April 2016,

Topic : Design of 512-Bit Ladner Fishner Adder

Authors:K.Sinduja || S.M.Dinesh , M.Vinisha , N.Devi Priya

Abstract:To make addition operations additional economical parallel prefix addition may be a higher technique. during this paper 64-bitparallel prefix addition has been enforced with the assistance of cells like black cell and gray cell operations for carry generation and propagation. This method offers high speed computations with high fan-out and makes carry operations easier. ISE Design suit 14.5 tool has been used for the simulation of projected 512-bit adder. The comparison are often created with the help numerous vary of inputs conjointly. The projected parallel prefix adder has made high speed computation and also efficient in terms of range of transistors and their topology and range of nodes..

Keywords: Ladner Fishner Adder,bitparallel prefix,cells,computation

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DOI: 01.1617/vol3iss4pid190


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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IMPACT FACTOR: 3.689

ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
ORCiD Research ID : 0000-0001-9540-6799

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