International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume3,May 2016,

Topic : ASIC Implementation of Data Comparison Circuit for Cache Memory

Authors:Basavaraj Mirji || R Pramod , Dr. V. Anandi

Abstract:In current scenario, computing system of microprocessor involves data comparison circuit for matching input data to the stored data in memory. For protection of data and to improve reliability, the recent microprocessor uses error correcting code. In this paper a new architecture for data matching is presented to reduce the delay and hardware circuit complexity. Taking into account the property of the systematic codeword, the deliberate shape comprising of information and parity bits independently, so parallel examination of information and parity bits diminishes the delay of the overall circuit..

Keywords: Data comparison, set associative cache, error correcting code (ECC), ASIC, Hamming Distance

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DOI: 01.1617/vol3iss5pid284


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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IMPACT FACTOR: 3.689

ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
ORCiD Research ID : 0000-0001-9540-6799

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