[1] Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, and Marco Ottavi, “A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems., vol. 32, no. 3, pp. 479 - 483, March 2013.

[2] Wei Wu, D Somasekhar, Shih.-Lien Lu “Direct compare of information coded with error correcting codes”, IEEE Trans. Very Large Scale Integr. Syst., vol. 20, no. 11, pp. 2147–2151, Nov. 2012.

[3] Current K W, Mow, Douglas A, “Implementing Parallel Counters with Four Valued Threshold Logic”, IEEE Transactions on computer, August 2006

[4] H. Ando, Y. Yoshida, A. Inoue, I. Sugiyama, T. Asakawa, K. Morita, T. Muta, T. Motokurumada, S. Okada, H. Yamashita, Y. Satsukawa, “A 1.3 GHz fifth generation SPARC64 microprocessor”, in IEEE ISSCC. Dig. Tech. Papers, Feb. 2003, pp. 246–247.

[5] Y. Lee, H. Yoo, I. C. Park “6.4Gb/s multi threaded BCH encoder and decoder for multi channel SSD controllers,” in ISSCC Dig. Tech. Papers, 2012, pp. 426- 427.

[6] S. Lin, D. J. Costello, “Error Control Coding Fundamentals and Applications”, 2nd ed. Englewood Cliffs, NJ, USA: Prentice-Hall, 2004.

[7] Caxton C, Foste, Fred D. Stockan, “Counting Responders in an Associative Memory”, IEEE Transactions on computer, December 1971.

[8] Brown, Frank M, “Weighted Realizations of Switching Functions”, IEEE transactions on computer, December 1975.