Author : Sanmati Kuthale 1
Date of Publication :7th May 2016
Abstract: This paper gives the hardware implementation of face detection on FPGA using HAAR features. The design consisting of integral image generation which is used to compute the HAAR features at a faster rate, has been illustrated. The classifiers are built using the Ada Boost algorithm which selects a minimum number of critical HAAR features from a very large set. Also, parallel processing classifiers increase the speed of the face detection system. The described detection architecture has been designed using Verilog HDL and implemented on Xilinx vertex-5 FPGA which shows optimization in terms of area and speed.
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