International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume3,June 2016,

Topic : Comparative Performance Analysis of CMOS Full Adders Using Various Pass Transistor Logic

Authors:Bore Gowda H B ||

Abstract:with the advancement in semiconductor technology, chip density and power consumption in VLSI circuits has become a major problem consideration. More area and power consumption increases the packaging cost and reduces the battery life of the devices. Hence itís necessary to design any VLSI circuits with less chip area and power consumption. In this paper an efficient full adder circuit is designed with various pass transistor logic families by using microwind simulating tool with CMOS 0.12?m processing technology. Microwind is truly integrated EDA software encompassing IC designs from concept to completion, enabling chip designers to design beyond their imagination. Microwind integrates traditionally separated front end and back end chip design into an integrated flow, accelerated the design cycle and reduced design complexity..

Keywords: Full Adder, CMOS, Power consumption, DPL, SRCPL, CP, ALU

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DOI: 01.1617/vol3iss6pid354


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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IMPACT FACTOR: 3.689

ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
ORCiD Research ID : 0000-0001-9540-6799

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