[1] Ahmed M. Shames, Tarek K. darwish and Magdy A. Bayoumi, "Performance Analysis of Low-Power 1-Bit CMOS Full Adder Cells", IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol.10, no.1, Feb.2002.

[2] Mariano Aguirre and Monico Linares, "An Alternative Logic Approach to Implement High-Speed Low-Power Full Adder"

[3] Sundeepkumar Agarwal, pavankumar V K and Yokesh R, "Energy-Efficient, High Performance Circuits for Arithmetic Units", IEEE DOI 10.1109/VLSI.2008.49.

[4] Nan Zhuang and Haomin W U, “A New Design of the CMOS Full Adder”, IEEE Journal of Solid-State Circuits, vol.27, no.5, May 1992.

[5] Reto Zimmermann and Wolfgang Fichtner, “LowPower Logic Styles: CMOS Verses Pass-Transistor Logic”, IEEE Journal of Solids-State Circuits, vol.32, no.7, Jul 1997.

[6] A. Shams, and M. Bayoumi, “Performance Evaluation of 1-bit CMOS Adder Cells”, IEEE, 1999.

[7] Eugene D Fabricius Introduction to VLSI Design. McGraw-Hill International Editions.

[8] Video reference: Low power VLSI Circuits and Systems by Prof. Ajit pal, Computer Science and Engineering, IIT Kharagpur. http://m.youtube.com/watch?v=x6iuqD94DOU