International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume3,June 2016,

Topic : Design and implementation of CMOS Domino Circuit for Low Power VLSI Applications

Authors:Aravind R || Manasa M G , Raju D H

Abstract:Dynamic logic style is used in high performance circuit design because of its fast speed of operation and less number of transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper we have proposed a novel circuit for domino logic which has less area and has less power-delay product (PDP) as compared to previous reported articles. Low PDP is achieved by using semidynamic logic buffer and also reducing leakage current when PDN is not conducting. Then comparison analysis has been carried out by simulating the circuits in 90nm CMOS process technology from TSMC using Tanner EDA 14.11..

Keywords: Dynamic logic, Dynamic Node, High speed, Diode Footed Domino, Noise Tolerance, Propagation delay, Power Consumption, Robustness, Domino CMOS logic.

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DOI: 01.1617/vol3iss6pid362


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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IMPACT FACTOR: 3.689

ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
ORCiD Research ID : 0000-0001-9540-6799

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