[1] B. Goll and H. Zimmermann, “A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 11, pp. 810–814, Nov. 2009.

[2] S. U. Ay, “A sub-1 volt 10-bit supply boosted SAR ADC design in standard CMOS,” Int. J. Analog Integr. Circuits Signal Process., vol. 66, no. 2, pp. 213–221, Feb. 2011.

[3] A. Mesgarani, M. N. Alam, F. Z. Nelson, and S. U. Ay, “Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS,” in Proc. IEEE Int. Midwest Symp. Circuits Syst. Dig. Tech. Papers, Aug. 2010, pp. 893–896.

[4] B. J. Blalock, “Body-driving as a Low-Voltage Analog Design Technique for CMO technology,” in Proc. IEEE Southwest Symp. Mixed-Signal Design, Feb. 2000, pp. 113–118.

[5] M. Maymandi-Nejad and M. Sachdev, “1-bi quantiser with rail to rail input range for sub-1V __ modulators,” IEEE Electron. Lett., vol. 39, no. 12, pp. 894–895, Jan. 2003.

[6] Y. Okaniwa, H. Tamura, M. Kibune, D. Yamazaki, T.- S. Cheung, J. Ogawa, N. Tzartzanis, W. W. Walker, and T. Kuroda, “A 40Gb/s CMOS clocked comparator with bandwidth modulation technique,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1680–1687, Aug. 2005.

[7] B. Goll and H. Zimmermann, “A 0.12 μm CMOS comparator requiring 0.5V at 600MHz and 1.5V at 6 GHz,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2007, pp. 316–317

[8] B. Goll and H. Zimmermann, “A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47μW at 0.6V,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp. 328–329

[9] B. Goll and H. Zimmermann, “Low-power 600MHz comparator for 0.5 V supply voltage in 0.12 μm CMOS,” IEEE Electron. Lett., vol. 43, no. 7, pp. 388–390, Mar. 2007

[10] D. Shinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, “A double-tail latch-type. Voltage sense amplifier with 18ps Setup+Hold time,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2007, pp. 314–315.

[11] P. Nuzzo, F. D. Bernardinis, P. Terreni, and G. Van der Plas, “Noise analysis of regenerative comparators for reconfigurable ADC architectures,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp. 1441–1454, Jul. 2008.