International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume3,July 2016,

Topic : ASIC Implementation of 32-bit MIPS RISC Processor using Multi-VDD Technique

Authors:Jeyakumar R || Suryavanshi Rushank Sharad , David Jey Singh , Jayakrishnan P

Abstract:the phenomena of scaling down the device results into certain hazards in the processor However it can have an adverse impact on the various performance parameters of the processor as area, power and timing. However in order to overcome the enlisted shortcomings the design of Microprocessor without Interlocked Pipeline Stages (MIPS) architecture is preferred. The Microprocessor without Interlocked Pipeline Stages is a RISC processor. The architecture discussed is implemented using Verilog HDL. Further ASIC flow is performed using 32nm technology. However low power realization is achieved by using multiple voltage (Multi-VDD) technique where by the critical path in the design is analyzed and the voltage of that respective path is increased there by achieving a good speed up..

Keywords: Technology; Instruction Set; MIPS; Pipeline; RISC; Verilog HDL

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DOI: 01.1617/vol3iss7pid395


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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IMPACT FACTOR: 3.689

ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
ORCiD Research ID : 0000-0001-9540-6799

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