Author : B.Raju 1
Date of Publication :7th August 2016
Abstract: This paper is about a parallel single-rail self-timed adder. It is based on a recursive formula method for performing 4- bit binary addition. we can have the parallel operation for the bits that do not need any carry chain propagation. Hence the design having logarithmic performance over random operand conditions without any special speedup circuitry or carry look-ahead schema. We can have a practical implementation is provided along with a completion detection unit. The implementation is regular and does not have any practical limitations of high fan-out. A high fan-in gate is required and we can avoid for asynchronous logic by connecting the transistors in parallel. Simulations have been performed using an industry standard toolkit h-spice that verifies the practicality and superiority of the proposed approach over existing asynchronous adders.
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