International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume3,October 2016,

Topic : Implementation and Analysis of Sign Extension and Baugh WOOLEY Multiplier in Ant Architecture

Authors:Vallem Hari Charan || B Leela Kumari

Abstract:Multiplier is the most crucial part in any digital signal processing (DSP) system applications. Designing a reliable multiplier in the deep submicron era is a challenging task. Deep sub micron technology needs low power, high signal to noise ratio, reliability and etc. There exists always a trade of between low power and reliability. The approach in this paper is to compromise both the reliability and low power in designing a multiplier. This paper deals with, implementation of reliable low power multiplier for signed bits and performance analysis of sign extension and Baugh wooley multipliers in ANT (Algorithmic Noise Tolerant) architecture with fixed width RPR block..

Keywords: ANT architecture, Sign Extension Multiplier, Baugh Wooley multiplier.

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DOI: 01.1617/vol3iss10pid480


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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IMPACT FACTOR: 3.689

ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
ORCiD Research ID : 0000-0001-9540-6799

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