FPGA Based Solution for Filtering of Data Generated Through DDS
Author : Ms. Rekha B 1
Date of Publication :18th May 2017
Abstract: This paper is concerned with removing the unwanted noise signal present in the original signal by using the digital (FIR) filter whose cut off frequency is 2.5Mhz.The input signal to the filter is generated using DDS IP core. The whole design is simulated and synthesized using Xilinx ISE Design suite 14.1 version and verified using the Matlab
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