Author : Deepthi R Shetty 1
Date of Publication :24th May 2017
Abstract: Arithmetic and logic unit (ALU) is a part of central processing unit that carries out arithmetic and logical operations and consists of many computational units like adders, multipliers, logic unit etc. In this review paper, ALU based on reversible logic gates and Vedic Mathematics concepts are discussed. Here reversible logic gates are used instead of the basic logic gates such as AND, OR etc which will function in the same way as that of the basic logic gates. An important requirement of digital system is to reduce power dissipation. By using reversible ALU instead of using basic logic gates power consumption is lowered. Also a high speed 8x8 bit multiplier based on Vedic multiplier mechanism is explained.
Reference :
-
- R. Landauer, Irreversibility and heat generation in the computing process, IBM Journal of Research and Development, 5(3), 1961, 183–191.
- C.H. Bennett, Logical reversibility of computation, IBM Journal of Research and Development, 17(6), 1973, 525–532.
- L. Viswanath and M. Ponni, Design and analysis of reversible ALU, IOSR Journal of Computer Engineering (IOSRJCE), 1(1), 2012, 46–53.
- Rahul Nimje, Sharda Mungale, “Design of arithmetic unit for high speed performance using Vedic mathematics, International Journal of Engineering Research and Applications, April 2014, pp 26 – 31.
- Abhishek Gupta, Utsav Malviya, Vinod Kapse, “A novel approach to design high speed arithmetic logic unit based onancient vedic multiplication technique”,International Journal of Modern Engineering Research, Vol. 2, no. 4, July, 2012, pp 2695 – 2698.
- S.P.Pohokar, R.S.Sisal, K.M.Gaikwad, M.M.Patil, Rushikesh Borse, “Design and Implementation of 16 x 16Multiplier Using Vedic Mathematics”, Proc of International Conference on Industrial Instrumentation and Control (ICIC), IEEE, 28-30 May 2015.
- Abhyarthana Bisoyil, Mitu Baratl, Manoja Kumar Senapati, “Comparison ofa 32-Bit Vedic Multiplier With AConventional Binary Multiplier”, Proc of IEEE International Conference on Advanced Communication Control and Computing Technologies (lCACCCT), 8-10 May 2014, pp 1757 – 1760.
- H.G. Rangaraju, U. Venugopal, K.N. Muralidhara, K.B. Raja, Low power reversible parallel binary adder/subtractor, International Journal of Scientific and Engineering Research,1(3), 2010, 23–34.
- A. Peres, Reversible logic and quantum computers, Physical Review, 32(6), 1985, 3266–3267.
- R. Feynman, Quantum mechanical computers, Foundations of Physics, 16(6), 1986, 507–531.
- M. Haghparast, S.J. Jassbi, I.K. Navi, and O. Hashemipour, Design of a novel reversible multiplier circuit using HNG gate in nanotechnology, World Applied Sciences Journal, 3(6), 2008, 974–978.E.
- Fredkin and T. Toffoli, Conservative logic, International Journal of Theoretical Physics, 21, 1980, 219– 53.