Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Implementing Vedic Formula for Square Computation in FPGA - A Survey

Author : Subrahmanya Bhat K G 1 Dr. Jose Alex Mathew 2

Date of Publication :10th May 2017

Abstract: The performance of any processor depends upon its speed, area and delay. Vedic mathematics is an ancient mathematics that has a unique method of computation based on simple rule. This paper reviews Vedic mathematics based high speed operations. The Vedic formula Dwandwa Yoga or Duplex squarer is based on duplex property which is used for squaring of numbers.

Reference :

    1. [K. R. Gavali and P. Kadam, "VLSI design of high speed Vedic Multiplier for FPGA implementation," 2016 IEEE International Conference on Engineering and Technology (ICETECH), Coimbatore, 2016, pp. 936-939.
    2. S. Sabeetha, J. Ajayan, S. Shriram, K. Vivek and V. Rajesh, "A study of performance comparison of digital multipliers using 22nm strained silicon technology," 2015 2nd International Conference on Electronics and Communication Systems (ICECS), Coimbatore, 2015, pp. 180-184.
    3.  R. Sharma, M. Kaur and G. Singh, "Design and FPGA implementation of optimized 32-bit Vedic multiplier and square architectures," 2015 International Conference on Industrial Instrumentation and Control (ICIC), Pune, 2015, pp. 960-964.
    4. V. Kunchigi, L. Kulkarni and S. Kulkarni, "Low Power Square and Cube Architectures Using Vedic Sutras," 2014 Fifth International Conference on Signal and Image Processing, Jeju Island, 2014, pp. 354-358.

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