Author : Laxman Marasini 1
Date of Publication :22nd May 2017
Abstract: Currently the speed of the multipliers is limited by the speed of the adders used for partial product addition. We proposed an 8-bit multiplier using a Vedic Mathematics (Urdhva Tiryagbhyam sutra) for generating the partial products. The product addition in Vedic multiplier is realized using partial products in parallel. An 8-bit multiplier is realized using a 8 and 12 bit parallel adders. In the proposed design we have reduced the number of logic levels, thus reducing the logic delay. Simulation of the architecture is synthesized using Xilinx ISE9.1.The performance of the proposed multiplier has been compared with those other multipliers reported in literature.
Reference :
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