Date of Publication :13th July 2017

Abstract: Cryptography plays an important role in the security of data. Encryption ensures data integrity by protecting the data from being corrupted or modified.RSA and DSA are the most commonly used methods for the authentication. Encryption uses symmetric and asymmetric encryption algorithms such as Triple-DES and Blowfish for maintaining the confidential. The AES is widely used for encryption of audio/video data contents in real time. Due to the significance of the AES algorithm and the numerous real-time applications, the main concern of this paper is to present new efficient hardware implementations for this algorithm.AES uses four operations, namely SubBytes, ShiftRows , MixColumns and Key Additions transformations. SubBytes transformation is done through S-BOX. This paper describes full custom design of high speed S-BOX for AES encryption algorithm and its implementation in FPGA and ASIC. The proposed AES architecture has delayed improvement of approx. 1.6 ns along with area improvement of 287 FPGA slices when implemented in the Spartan-6 FPGA of Xilinx. The full custom design of the S-BOX has been done in 180 nm technology in Cadence using novel XOR gate which has high speed and low power consumption . The designed S-BOX chip consumes 22.6 μW and has 8.2 ns delay after post layout simulation

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