Author : Akshata G. Shete 1
Date of Publication :16th August 2017
Abstract: This paper describes new technique for area and power evaluation 6T latch for shift register. In this technique area and power optimized by using pulsed latch instead of flip flop. Pulsed latch causes the timing problem which is overlapped in conventional single pulse clock. Here we are using non-overlapped delayed clock signal to solve this problem. The advanced portable devices require area and power efficient devices. The design is implemented with 65nm technology in Micro wind EDA (Electronic Design Automation) Tool. A n-bit shift register using pulsed latches is designed. The simulation results show that the proposed shift register design with less transistor count is better choice for low power and area efficient applications.
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