Date of Publication :21st August 2017
Abstract: An Implicit Pulse Triggered D flip flop is designed, which incorporates gated clocking. Clock gating using XOR gate inhibits redundant internal node switching. The pull-up network (PUN) control technique is used to conditionally strengthen the discharge path. This work aims at further reduction in power consumption using substrate bias technique to reduce leakage power which is referred to as Back Gate Forward/Reverse Bias method. Cadence Virtuoso 180nm technology is used to implement various pre & post layout simulations. From the results, it can be inferred that the proposed design reduces the power consumption by 41.82% at 10% data switching activity as compared with the existing counterparts. A comparison of three bit counter designed using conventional transmission gate (TG) based master-slave flip-flop and the proposed implicit pulse triggered flip flop shows a reduction of 23.90% in average power consumption.
Reference :
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