Author : Reshma Ghurde 1
Date of Publication :20th August 2017
Abstract: This paper present Distributed Arithmetic (DA) Algorithm for high-throughput reconfigurable implementation of an FIR Filter. When we directly applied the DA algorithm to FPGA for realization of an FIR filter, it is difficult to achieve the best configuration in the coefficient of FIR filter, the storage resource and the computing speed. For the FPGA implementation, the Dual-Port Distributed RAM based lookup table (LUT) are required for Reconfigurable FIR Filter. Registers are required to store the result of partial inner products of different bit positions for DA processing, but here registers are shared by the DA units for bit slices of different weightage
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