Author : Linumon Thomas 1
Date of Publication :14th June 2017
Abstract: Power reduction is of significant importance in VLSI designs. As VLSI technology goes further in nanometer technology, as speed increases power becomes an important parameter. There are various design techniques which can be used to reduce power. Optimization in synthesis and physical design stages can give significant power reduction. In this paper, power reduction through optimization of clock network in digital circuits is discussed.
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