Open Access Journal

ISSN : 2394-6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

A comparative study of Excess Loop Delay Compensation Techniques in Continuous Time Delta- Sigma Modulators

Author : Aditi Singh 1 Kumaravel S 2

Date of Publication :17th August 2017

Abstract: Continuous time ∑∆ Convertor is an highly power efficient modulator which has overcome the pipeline and Discrete time modulator as they require more number of high speed gain stages.Morever it is has an aliasing free Nquist band which is made available by oversampling and an on chip filter is also present.The input is resistive with no sampling so it is easier to drive the entire modulator with miniscule noise and an on- chip clock conditioner is used.There are several drawbacks associated with CTDSM like clock jitter and excess loop delay.In this paper different techniques to reduce Excess Loop Delay(ELD) in a continuous time delta sigma modulator is analysed and presented.

Reference :

  1. [1] Delta Sigma Data convertors by Steven R Norsworthy,RichardSchreier,Gabor C Temes, IEEE Press.

    [2] High-Speed Data Conversion Using ContinuousTime Delta-Sigma Modulators by James A. Cherry.

    [3] Excess Loop Delay Compensation in ContinuousTime Delta-Sigma Modulators -Shanthi Pavan.

    [4] A Continuous-Time ΔΣADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation-Yue Hu, HariprasathVenkatram, Nima Maghari, and Un-Ku Moon

    [5] A 400 MHz Delta-Sigma Modulator for BandpassIF Digitization Around 100 MHz With Excess Loop Delay Compensation -AkhilGupta, Shahrokh Ahmadi, Mona Zaghloul Department of Electrical and Computer Engineering The George Washington University Washington, DC, USA

    [6] Extra Loop Delay Compensation for Hybrid DeltaSigma Modulators Yusaku Hirai, Kenji Ohara, and Toshimasa Matsuoka Graduate School of Engineering Osaka University, Osaka, Japan

    [7] A Novel Excess Sturdy-MASH-Loop-Delay Compensated Cross-Coupled Modulator, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded SystemsJ. Clerk Maxwell, A Treatise on Electricity and Magnetism, 3rd ed., vol. 2. Oxford: Clarendon, 1892, pp.68-73.

    [8] David A.Johns, Ken Martin, “Analog Integrated Circuit Design” John Wiley & Sons In.

    [9] Behzad Razavi, “Principles of Data Conversion System Design” Wiley-IEEE Press

    [10] R.Jacob Baker “CMOS circuit design layout and stimulation”,IEEE Press

    [11]Understanding Delta Sigma Convertors,by Shanti Pawan,Richard Schreier,Gabor C.Temes.

    [12] US Patent Pipelined delta sigma modulator analog to digital converter ,US 20050083220 A


Recent Article