Author : Kishore Kumar K 1
Date of Publication :17th August 2017
Abstract: The primary downside of utilizing CMOS transistors is high power utilization and high leakage current. FinFET has turned into the most encouraging substitute for CMOS which has less short channel effects compared to CMOS technology. In low power applications, as the technology is scaling down leakage current and leakage power are the most noticeable problems for SRAM cell. The interest for static random access memory (SRAM) is expanding with extensive utilization of SRAM in System On- Chip and VLSI circuits. In order to design low power devices leakage current and power dissipation must be kept low. To reduce this dissipation conventional 12T SRAM is implemented using FinFET technology. In this paper power consumption during hold, read and write operations of CMOS 12T SRAM cell with FinFET based 12T SRAM cell are compared with the help of HSPICE simulator
Reference :
-
[1] Satyendra Kumar, Vinay Anand Tikkiwal, Rariom Gupta “Read SNM Free SRAM Cell Design in Deep Sub micron Technology”. 2013 International Conference on Signal Processing And Communication (Icsc).
[2] Vivek kumar, Vikas Manohar and Manisha Pattanaik “Novel Ultra Low Leakage FinFET Based SRAM Cell”. 2016 IEEE International Symposium on Nanoelectronic and Information Systems.
[3] G.Boopathi Raja, M.Madheswaran, “Design and Performance Comparison of 6-T SRAM Cell in 32nm CMOS, FinFET and CNTFET Technologies”. International Journal of Computer Applications, 2013.
[4] Priya Thakare, Sanjay Tembhurne “A Power Analysis of SRAM Cell Using 12T Topology for Faster Data Transmission: A Review”. International Research Journal of Engineering and Technology (IRJET), 2016.
[5] S.A. Tawfik and V. Kursun, “Low Power and Stable FinFET SRAM with Static Independent Gate Bias for Enhanced Integration Density”, 14th IEEE International conference on electronics, circuits and systems.
[6] Aly, R. E., Bayoumi, M. A ,"Low-Power Cache Design Using 7T SRAM Cell," IEEE Transactions On Circuits And Systems-II: Express Briefs, Vol. 54, No. 4, April 2007.
[7] V.Gupta and M.Anis, Member, IEEE "Statistical Design ofthe 6T SRAM bit Cell," IEEE Transactions On Circuits And Systems-I: Regular Papers, Vol. 57, No. 1 , January 2010 .
[8] V.Gupta and M.Anis, Member, IEEE "Statistical Design ofthe 6T SRAM bit Cell," IEEE Transactions On Circuits And Systems-I: Regular Papers, Vol. 57, No. 1 , January 2010 .
[10] Ambrish Mall, Suryabhan Pratap Singh, Manish Mishra, Geetika Shrivastava, “Analysis Of 12t Sram Cell For Low Power Application” Deportment of Electronics, DDUGU Gorakhpur (273009),(U.P), INDIA. Amity School of engineering & Technology.
[11] K.G.Dharani,“Comparative Analysis of 6 Transistor, 8 Transistor and 12 Transistor SRAM Memories” Research Scholar,Karpagam University, Coimbatore Tamilnadu, India.