Date of Publication :13th September 2017
Abstract: With continuous increase in number of transistors placed on single chip and continuous decrease in minimum feature size of transistors has led to significant increase in device density and device complexity at cost of power demand, has brought need of power optimization in such chips with most common implementation in VLSI (Very Large Scale Integration) circuits. VLSI circuits are both combinational and sequential circuits in nature. But in case of sequential circuits, clock is major source of power consumption. This paper proposes Clock Gating technique to decrease clock power consumption by cutting off ideal clock cycles. Here, a VHDL based technique is used to insert clock gating circuit and dynamic power is calculated and thereafter, model has been implemented onto ISCAS’89 benchmark circuit compiled by Modalism Alters 13.1 and Xilinx ISE tool for simulating and analyzing power and results obtained revels that dynamic power is reduced for sequential circuits.
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