Author : Z Dorababu 1
Date of Publication :12th September 2017
Abstract: In the previous average-8T static random access memory has a competitive area and does not require a write-back scheme. In the case of average 8T SRAM architecture, a full-swing local bitline, that can be achieved with a boosted wordline voltage. In this average 8T SRAM Architecture, such as a 22-nm FinFET technology used, where the variation in threshold voltage is large, because of this reason read stability of SRAM degraded. Thus, a full-swing local BL cannot be achieved, resulting in a considerably large read delay and it can store only four bits in one block. To overcome the above disadvantages, in this paper and proposed SRAM architecture with a full swing local BL is proposed. In the proposed SRAM architecture, full swing of the local BL is ensured by the use of cross-coupled pMOSs, and the gate of the read buffer is driven by a full VDD, without the need for the boosted WL voltage. The proposed SRAM architecture that stores 16 bits in one block with achieves with 0.8v minimum voltage and read delay is lesser than that of average 8T SRAM architecture.
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