Date of Publication :17th November 2017

Abstract: The design for testability is increased by constructing flip flops using transmission gates. The multiplexer serves as the switching circuit between the normal mode and the testing mode. The normal mode depicts the exact condition of the circuit when the primary inputs are given; the primary outputs are derived from the circuit. The testing mode is based on the switching activity of the circuit and its response is analyzed. The switching activity is based on the transitions produced by the test pattern given during the test mode. The proposed method provides a reduced power due to the usage of transmission gates. This shows a wide range of improvements through the optimization of the basic multiplexer logic along with the flip flops. The circuit was simulated and synthesized using Tanner EDA tool and the power analysis was done. There was a significant reduction in the power consumption.

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