Author : Mangala. S. Jolad 1
Date of Publication :8th January 2018
Abstract: In Digital Integrated Circuits, Adders are the most widely used digital components for computing applications. In this paper 8-bit Carry Bypass Adder and Carry Increment Adder are implemented using Xilinx and CADANCE tool. The performance parameters such as area, delay and power distribution are discussed.
Reference :
-
- Jasbir Kaur, Lalit Sood “Comparison Between Various Types of Adder Topologies” IJCST Vol. 6, Iss ue 1, Jan - March 2015.
- Massimo Alioto and Gaetano Palumbo “Optimized Design of Carry-Bypass Adders” August 28-31, 2001.
- Aribam Balarampyari Devi, Manoj Kumar and Romesh Laishram “Design and Implementation of an Improved Carry Increment Adder”
- ISHMEET SINGH, MANIKA DHINGRA “ Design and Implementation of 32-Bits Carry Skip Adder using CMOS Logic in Virtuoso, Cadence” Vol.03, Issue.07, September2015, Pages:1116-1121
- Nagaraj Y, Shrinivas K, Veeresh K, Veeresh A, Madhu Patil, Dr.Chirag Sharma “FPGA implementation of different adder architectures” Volume 2, Issue 8, August 2012
- Rajender Kumar, Sandeep Dahiya “Performance Analysis of Different Bit Carry Look Ahead Adder Using VHDL Environment”. Volume 2, Issue 4, July 2013.
- Yedukondala Rao Veeranki, Alok Katiyar, Venkata Reddy Kopparthi “Carry Bypass & Carry Select Adder Using Reversible Logic Gates” Volume 2 Issue 4 April, 2013 Page No. 1156-1161.
- Reto Zimmermann and Hubert Kaeslin “Cell-Based Multilevel Carry-Increment Adders with Minimal AT- and PT-Products”
- Deepa Sinha, Tripti Sharma, k.G.Sharma, B.P.Singh, “Design and Analysis of low Power 1-bit Full Adder Cell”, IEEE, 2011.
- B. Ramkumar and H. M. Kittur, “Low-power and areaefficient carry-select adder,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2, pp. 371–375, Feb. 2012
- Maroju SaiKumar, and Dr. P. Samundiswary, "Design and Performance Analysis of Various Adders using Verilog," International Journal of Computer Science and Mobile Computing, vol. 2, pp. 128-138, September 2013.
- Sajesh Kumar U., Mohamed Salih K. K, Sajith K “ Design and Implementation of Carry Select Adder without Using Multiplexer ” International Conference on Emerging echnology Trends in Electronics, Communication and Networking, Volume 3, Issue 8, August 2013. 13.Konstantinos Vitoroulis and Asim J. Al-Khalili “Performance of Parallel Prefix Adders implemented with FPGA technology” IEEE 2007.
- A.Prabhu, K.Pradeepa giri, R.Ranjitha “Implementation of multiple bit carry look ahead adder using verilog platform” Vol.3, No.7, July 2014.
- B. Ramkumar and Harish M Kittur “Low-Power and Area-Efficient Carry Select Adder” IEEE Trans. on very large scale integration systems 2011.