Open Access Journal

ISSN : 2394-6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Data Encoding Techniques for Reducing Energy Consumption in Network-On-Chip

Author : G.Manasa 1 A.Mounika 2

Date of Publication :14th February 2018

Abstract: In this paper, we display an arrangement of information encoding plans went for diminishing the power disseminated by the connections of a NoC. As innovation recoils, the power disseminated by the connections of a system-on-chip (NoC) begins to contend with the power dispersed by alternate components of the correspondence subsystem to be specific the switches and the system interfaces (NIs). The proposed plans are general and straightforward regarding the hidden NoC texture (i.e., their application does not require any adjustment of the switches and connection design). Examinations completed on both engineered and genuine movement situations demonstrate the adequacy of the proposed plans, which permit setting aside to 51% of energy scattering and 14% of vitality utilization with no huge execution corruption and with under 15% territory overhead in the system interface. The EDA instrument utilized as a part of the paper is Software apparatuses i.e. Modalism 10.0c (Simulation), Xilinx ISE 14.4 (Synthesis) and dialects utilized for yields is Verilog-HDL

Reference :

    1. Young-Ho Seo and Dong-Wook Kim, "New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm," IEEE Transactions on very large scale integration (VLSI) systems, vol. 18, no. 2,february 2010.
    2. Ron S. Waters and Earl E. Swartzlander, Jr., "A Reduced Complexity Wall ace Multiplier Reduction, " IEEE Transactions On Computers, vol. 59, no. 8, Aug 2010.
    3. C. S. Wallace, "A suggestion for a fast multiplier," IEEE Trans. Electron Comput., vol. EC-13, no. I, pp. 14-17, Feb. 1964.
    4. Shanthala S, Cyril Prasanna Raj, Dr.S.Y.Kulkarni, "Design and VLST Implementation of Pipelined Multiply Accumulate Unit," IEEE International Conference on Emerging Trends in Engineering and Technology, ICETET09.
    5. B.Ramkumar, Harish M Kittur and P.Mahesh Kannan, "ASIC Implementation of Modified Faster Carry Save Adder ", European Journal of Scientific Research, Vol. 42, Issue 1, 2010
    6. R.UMA, Vidya Vijayan, M. Mohanapriya and Sharon Paul, "Area, Delay and Power Comparison of Adder Topologies", International Journal of VLSI design & Communication Systems (VLSI CSj Vo1.3, No.1, February 2012.
    7. V. G. Oklobdzija, "High-Speed VLSI Arithmetic Units: Adders and Multipliers", in "Design of High-Performance Microprocessor Circuits", Book edited by A.Chandrakasan, IEEE Press, 2000
    8. Dadda, "Some Schemes for Parallel Multipliers," Alta Frequenza, vol. 34, pp. 349-356, 1965.
    9. C.S. Wall ace "A Suggestion for a fast multipliers," IEEE Trans. Electronic Computers, vol. 13, no.l, pp 14-17, Feb. 1967
    10. L.Dadda, "On Parallel Digital Multiplier", Alta Frequenza, vol. 45, pp. 574-580, 1976.
    11. WJ. Townsend, E.E. Swartzlander Jr., and J.A. Abraham, "A Comparison of Dadda and Wall ace Multiplier Delays," Proc.SPIE, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, pp. 552-560, 2003.
    12. Fabrizio Lamberti and Nikos Andrikos, " Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers", IEEE transactions on computers, Vol. 60, NO. 2, FEBRUARY 2011

Recent Article