Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering
Call For Paper : Vol 11, Issue 08, August 2024

ISSN : 2394-6849 (Online)

Call for Paper

Vol 11, Issue 08, August 2024

Indexing

Single Phase Clock Distribution Using Low power and Multiband Pre-scalar

Author : M.Mounika 1 Md.Rubeena 2

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Date of Publication :21st February 2018

Abstract: Regularly the clock circulation system will devour around 70% of the aggregate power devoured by the IC since this is the main flag which has the most elevated action. Fundamentally for a multi-clock area organize we build up a various PLL to cook the need, yet it devours more power. Thus, the fundamental point of this task is building up a low power single clock multiband arrange which will supply for the multi-clock space organize. It is very valuable and prescribed for correspondence applications like Bluetooth, Zigbee, and WLAN. It is demonstrated utilizing Verilog mimicked utilizing Modalism and actualized in Xilinx

Reference :

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    1. P. Y. Deng et al., “A 5 GHz frequency synthesizer with an injection locked frequency divider and differential switched capacitors,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 2, pp. 320–326, Feb 2009.
    2. P. Y. Deng et al., “A 5 GHz frequency synthesizer with an injection locked frequency divider and differential switched capacitors,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 2, pp. 320–326, Feb 2009.
    3. M. Alioto and G. Palumbo, Model and Design of Bipolar and MOS Current-Mode Logic Digital Circuits. New York: Springer, 2005.
    4. H.R.Rategh et al., "A CMOS frequency synthesizer with an injected locked frequency divider for 5-GHz wireless LAN receiver," IEEE J. Solid-State Circuits, vol. 35, no.5, pp. 780-787, May 2000.
    5. L. S. Y. Wong and G. A. Rigby, “A 1V CMOS digital circuits with double-gate-driven MOSFET,” in Proc. IEEE ISSCC97, pp. 292– 293.
    6. N. Lindert, T. Sugii, S. Tang, and C. Hu, “Dynamic threshold pass-transistor logic for improved delay at low power supply voltages,” IEEE J.Solid-State Circuits, vol. 34, pp. 85–89, Jan. 1999.
    7. C. Y. Yang, G. K. Dehng, J. M. Hsu, and S. I. Liu, “New dynamic flip-flops for high-speed dual-modulus prescaler,” IEEE J. Solid-State Circuits, vol. 33, pp. 1568–1571, Oct. 1998.
    8. B. Chang, J. Park, and W. Kim, “A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flipflops,” IEEE J. Solid-State Circuits, vol. 31, pp. 749–752, May 1996.
    9. “Nippon Precision Circuits Inc. datasheet,” Nippon Precision Circuits Inc., Tokyo, Japan, SM5160CM/DM, 1996.
    10. M. J. Chen, J. S. Ho, T. H. Huang, C. H. Yang, Y. N. Jou, and T. Wu, “Back-gate forward bias method for lowvoltage CMOS digital circuits,” IEEE Trans. Electron Devices, vol. 43, pp. 904–909, June 1996

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