Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

DSP Accelerator Architecture Using Carry-Save Arithmetic

Author : E. Ramya 1 Roja. S 2 Roja.R 3 Sandhiya.G 4

Date of Publication :19th April 2018

Abstract: A high-performance data path to implement DSP kernels are introduced in this paper. Hardware acceleration has been proved an extremely promising implementation DSP domain. We present a novel accelerator architecture comprising flexible computational units for the execution of a large set of operation templates in DSP kernels. Carry Save method has been implemented to improve the performance of the accelerator while computing more bits. Advanced arithmetic design concepts, i.e., recording techniques, are utilized enabling CS optimizations to be performed in a larger scope than in previous approaches. Accelerator architecture delivers average gain compared with the state-of-art flexible datapaths.

Reference :

    1. P. Ienne and R. Leupers, Customizable Embedded Processors: Design Technologies and Applications. San Francisco, CA, USA: Morgan Kaufmann, 2007.
    2. P. M. Heysters, G. J. M. Smit, and E. Molenkamp, “A flexible and energy-efficient coarse-grained reconfigurable architecture for mobile systems,” J. Supercomput., vol. 26, no. 3, pp. 283–308, 2003.
    3. B. Mei, S. Vernalde, D. Verkest, H. D. Man, and R. Lauwereins, “ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix,” in Proc. 13th Int. Conf. Field Program. Logic Appl., vol. 2778. 2003, pp. 61–70.
    4. M. D. Galanis, G. Theodoridis, S. Tragoudas, and C. E. Goutis, “A high-performance data path for synthesizing DSP kernels,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 6, pp. 1154– 1162, Jun. 2006
    5. . K. Compton and S. Hauck, “Automatic design of reconfigurable domain- specific flexible cores,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 5, pp. 493–503, May 2008
    6. S. Xydis, G. Economakos, and K. Pekmestzi, “Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths,” Integr., VLSI J., vol. 42, no. 4, pp. 486–503, Sep. 2009.
    7. S. Xydis, G. Economakos, D. Soudris, and K. Pekmestzi, “High perfor- mance and area efficient flexible DSP datapath synthesis,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 3, pp. 429–442, Mar. 2011.
    8. G. Ansaloni, P. Bonzini, and L. Pozzi, “EGRA: A coarse grained reconfigurable architectural template,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 6, pp. 1062–1074, Jun. 2011.
    9. M. Stojilovic, D. Novo, L. Saranovac, P. Brisk, and P. Ienne, “Selective flexibility: Creating domain-specific reconfigurable arrays,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 32, no. 5, pp. 681–694, May 2013.
    10. R. Kastner, A. Kaplan, S. O. Memik, and E. Bozorgzadeh, “Instruction generation for hybrid reconfigurable systems,” ACM Trans. Design Autom. Electron. Syst., vol. 7, no. 4, pp. 605–627, Oct. 2002.
    11. .T. Kim and J. Um, “A practical approach to the synthesis of arithmetic circuits using carry-save-adders,” IEEE Trans. Comput.- Aided Design Integr. Circuits Syst., vol. 19, no. 5, pp. 615–624, May 2000.
    12. Hosangadi, F. Fallah, and R. Kastner, “Optimizing high speed arithmetic circuits using three-term extraction,” in Proc. Design, Autom. Test Eur. (DATE), vol. 1. Mar. 2006, pp. 1–6.
    13. K. Verma, P. Brisk, and P. Ienne, “Data-flow transformations to maximize the use of carry-save representation in arithmetic circuits,” IEEE Trans. Comput.- Aided Design Integr. Circuits Syst., vol. 27, no. 10, pp. 1761–1774, Oct. 2008.
    14. S. Xydis, G. Palermo, and C. Silvano, “Thermal-aware datapath merging for coarse-grained reconfigurable processors,” in Proc. Design, Autom. Test Eur. Conf. Exhibit. (DATE), Mar. 2013, pp. 1649–1654.
    15. M. Srinivasaperumal, G. Naveen Balaji, M. Jagadesh "Heterogenous Node Recovery from crash in wireless Sensor actor networks" International Journal of Modern Trends in Engineering and Science,Vol. 3, Issue 6 (2016) pp: 116-120, ISSN: 2348-3121
    16. G.Naveenbalaji, N.V.Harisuriya, S.Anandvikash, B.Adithya, S.Arunkumar "Cost effective power supply based on transformer-less circuitry using bridge rectifier" International Journal of Engineering Research,Vol. 4, Issue 3 (May June 2016) pp: 70-74, ISSN: 2321-7758
    17. G. Naveen Balaji, S. Chenthur Pandian, D. Rajesh "A survey on effective Automatic Test Pattern Generator for self-checking Scan - BIST VLSI circuits" International Research Journal of Engineering and Technology,Vol. 3, Issue 5 (May 2016) pp: 645-648, ISSN: 2395 -0056
    18. G.Naveen Balaji, V.Aathira, K. Ambhikavathi, S. Geethiga, R. Havin "Combinational Circuits Using Transmission Gate Logic for Power Optimization" International Research Journal of Engineering and Technology,Vol. 3, Issue 5 (May 2016) pp: 649-654, ISSN: 2395 -0056
    19. R. ArunSekar, G. Naveen Balaji, A. Gautami, B. Sivasankari “High Efficient Carry Skip Adder in various Multiplier Structures” Advances in Natural and Applied Sciences (Annexure II), Vol. 10 Issue 14 (Special) (Oct 2016) pp: 193-197, ISSN: 1995-0772
    20. M. Srinivasaperumal, K. Boopathi Raja, G. Naveen Balaji, E. Christina Dally “Concurrent Node Recovery From Failure In Wireless Sensor-Actor Networks” KARI Research Journal, Vol. 1 Issue 4 (Oct - Dec 2016) pp: 28-33, ISSN: 2456-6136
    21. G. Naveen Balaji, V. Narayanan,V.S. Nivash “Low Power and High performance JK Flip – Flop using 45 nm Technology” International Journal of Engineering Research in Electronics and Communication Engineering (IJERECE) Vol 3, Issue 10, October 2016, pp:26-29, ISSN: 2394-6849
    22. M. Srinivasaperumal, K. Boopathi Raja, G. Naveen Balaji, E. Christina Dally “Concurrent Node Recovery From Failure In Wireless Sensor-Actor Networks” Advances in Natural and Applied Sciences (Annexure II), Vol. 10 Issue 17 (Dec 2016) pp: 240-246, ISSN: 1995- 0772
    23. G. Naveen Balaji, R. Prabha, E. Shanthini, J. Jayageetha, Mohand Lagha “Rapid low power Synchronous circuits using transmission gates” Advances in Natural and Applied Sciences (Annexure II), Vol. 10, Issue 17 (Dec 2016) pp: 287-291, ISSN: 1995-0772
    24. G. Naveen Balaji, S. Chenthur Pandian, D. Rajesh “Fast Test Pattern Generator using ATALANTA M 2.0” Asian Journal of Research in Social Sciences and Humanities (Annexure I) Vol. 7 No. 2 (Feb 2017) pp. 721- 729 ISSN: 2249-7315 DOI: 10.5958/2249-7315.2017.00124.1
    25. G. Naveen Balaji, V. Aathira, K. Ambhikavathi, S. Geethiga, R. Havin “Low Power and High Speed Synchronous Circuits using Transmission Gates” Asian Journal of Research in Social Sciences and Humanities (Annexure I), Vol. 7 No. 2 (Feb 2017) pp. 713-720. ISSN: 2249-7315, DOI: 10.5958/2249-7315.2017.00123.X
    26. G. Naveen Balaji, S. Anusha, J. Ashwini “GPS Based Smart Navigation for Visually Impaired Using Bluetooth 3.0” Imperial Journal of Interdisciplinary Research (IJIR) Vol. 3, No. 3, 2017, pp. 773-776. ISSN: 2454-1362
    27. G. Naveen Balaji, N.V. Hari Suriya, S. AnandVikash, R.Arun, S. Arun Kumar “Analysis of Various Liquid Components under Different Temperature and Density Constraints Pertaining To Fractional Distillation” Imperial Journal of Interdisciplinary Research (IJIR) Vol. 3, No. 6, 2017, pp. 664-669. ISSN: 2454-1362
    28. G. Naveen Balaji, D. Rajesh “Python Based Reverse Timing Algorithm for Human Brain Activity Using Color Psychology” International Journal of Indian Psychology, Vol. 4, No. 3, DIP: 18.01.111/20170403, pp: 79-86, ISSN 2348- 5396
    29. G. Naveen Balaji, S. Chenthur Pandian, D. Rajesh “High Performance Triplex Adder Using CNTFET” International Journal of Trend in Scientific Research and Development, Vol.1, No. 5, pp: 368-373, ISSN 2456 - 6470
    30. G. Naveen Balaji, S. Chenthur Pandian, S. Giridharan, S. Shobana, J. Gayathri “Dynamic and Non-Linear Charge Transfer Through Opto-Deportation by Photovoltaic Cell” International Journal of Trend in Scientific Research and Development, Vol. 1, No. 5, pp: 486-492, ISSN 2456 - 6470
    31. G. Naveen Balaji, S. Karthikeyan, M. Merlin Asha “ 0.18μm CMOS Comparator for High-Speed Applications” International Journal of Trend in Scientific Research and Development, Vol. 1, No. 5, pp: 671-674, ISSN 2456 - 6470
    32. G. Naveen Balaji, K. Saravanan, R. Poorani, T. Vishnu Priya, R. Reka Raj “Advanced Security System using PIC through Bluetooth” International Journal of Trend in Scientific Research and Development, Vol. 1, No. 5, pp: 675- 685, ISSN 2456 - 6470
    33. G. Naveen Balaji, N.V. Hari Suriya, S. Anand Vikash, S. Arun Kumar, R. Arun, “Gasoline Purity Meter Using Peripheral Interface Controller for Automobile Applications” International Journal of Engineering and Technical Research (IJETR), Vol. 7, No.10, pp:46-55, ISSN: 2321-0869
    34. G. Naveen Balaji, S.Chenthur Pandian, “Design for Testability of Kipbond Logic” “Perspectivas em Ciência da Informação” (Annexure - I), School of Information Science of the Federal University of Minas Gerais (UFMG), Vol. 22, No. SP.01, pp: 261-284, ISSN 1413-9936

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