Author : E. Ramya 1
Date of Publication :19th April 2018
Abstract: A high-performance data path to implement DSP kernels are introduced in this paper. Hardware acceleration has been proved an extremely promising implementation DSP domain. We present a novel accelerator architecture comprising flexible computational units for the execution of a large set of operation templates in DSP kernels. Carry Save method has been implemented to improve the performance of the accelerator while computing more bits. Advanced arithmetic design concepts, i.e., recording techniques, are utilized enabling CS optimizations to be performed in a larger scope than in previous approaches. Accelerator architecture delivers average gain compared with the state-of-art flexible datapaths.
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