Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering
Call For Paper : Vol 11, Issue 03, March 2024

ISSN : 2394-6849 (Online)

Call for Paper

Vol 11, Issue 03, March 2024

Indexing

Wirelength And Routability For Fixed Outline Networks

Author : S.P.Kalaiarasi 1 B.Srinath 2 P.Arunapriya 3

PDF

Date of Publication :25th May 2018

Abstract: In this paper, we propose an SKB-tree representation for the separation of multiple supply voltage (MSV) of modules in Integrated Circuits(IC) and routability at the same time under the fixed-outline constraint. Apart from previous works, we constrain modules of the same voltage to be placed into one region for wirelength optimization. This proposed methodology results, can reduce wirelength and be routing congestion in ICs. Our approach guarantees to obtain the minimum wirelength in time. The algorithm finds the position of modules in ICs to reduce the wirelength. It will dynamically allocate modules in fixed outline Integrated Circuits. This algorithm is implemented in GSRC bench circuits for wirelength optimization

Reference :

    1. J. Hu, Y. Shin, N. Dhanwada, and R. Marculescu, “Architecting voltage islands in core-based system-on-achip designs,” in Proc. ISLPED, 2004, pp. 180–185.
    2. W.-L. Hung, G. M. Link, Y. Xie, N. Vijaykrishnan, N. Dhanwada, and J. Conner, “Temperature-aware voltage islands architecting in system-on-chip design,” in Proc. ICCD, 2005, pp. 689–696.
    3. D. E. Lackey, P. S. Zuchowski, T. R. Bednar, D.W. Stout, S. W. Gould, and J. M. Cohn, “Managing power and performance for system-on-chip designs using voltage islands,” in Proc. ICCAD, 2002, pp. 195–202.
    4. W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, “Voltage island aware floorplanning for power and timing optimization,” in Proc. ICCAD, 2006, pp. 389–394.
    5. Q. Ma and E. F. Y. Young, “Multivoltage floorplan design,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 29, no. 4, pp. 607–617, Apr. 2010
    6. S. Nakatake, K. Fujiyoshi, H. Murata, and Y. Kajitani, “Module placement on BSG-structure and IC layout applications,” in Proc. ICCAD, 1996, pp. 484 491.
    7. D. Sengupta and R. Saleh, “Application-driven floorplan-aware voltage island design,” in Proc. DAC, 2008, pp. 155–160.
    8. L. Cheng, L. Deng, and M. D. F. Wong, “Floorplanning for 3-D VLSI design,” in Proc. ASP-DAC, Shanghai, China, Jan. 2005, pp. 405–411.
    9. R. Fischbach, J. Lienig, and J. Knechtel, “Investigating modern layout representations for improved 3D design automation,” in Proc. GVLSI, Lausanne, Switzerland, May 2011, pp. 337–342.
    10. J. Cong, J. Wei, and Y. Zhang, “A thermal-driven floorplanning algorithm for 3D ICs,” in Proc. ICCAD, San Jose, CA, USA, Nov. 2014, pp. 306–313.
    11. J. Knechtel, E. F. Y. Young, and J. Lienig, “Planning massive interconnects in 3-D chips,” IEEE Trans. Comput.- Aided Design Integr. Circuits Syst., vol. 34, no. 11, pp. 1808–1821, Nov. 2015.
    12. P. Zhou et al., “3D-STAF: Scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits,” in Proc. ICCAD, San Jose, CA, USA, Nov. 2007, pp. 590–597.
    13. C.-R. Li, W.-K. Mak, and T.-C. Wang, “Fast fixedoutline 3-D IC floorplanning with TSV co-placement,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 3, pp. 523–532, Mar. 2013.
    14. J. Z. Yan and C. Chu, “DeFer: Deferred decision making enabled fixedoutline floorplanning algorithm,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 3, pp. 367–381, Mar. 2010.
    15. S. Chen and T. Yoshimura, “Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints,” Integr. VLSI J., vol. 43, no. 4, pp. 378–388, Sep. 2010.
    16. C.-R. Li, W.-K. Mak, and T.-C. Wang, “Fast fixedoutline 3-D IC floorplanning with TSV co-placement,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 3, pp. 523–532, Mar. 2013.
    17. J. Z. Yan and C. Chu, “DeFer: Deferred decision making enabled fixedoutline floorplanning algorithm,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 3, pp. 367–381, Mar. 2010.
    18. W. Li, J. Kim, and J.-W. Chong, “A novel congestion estimation model and congestion aware floorplan for 3D ICs,” in Proc. ICIMTR, Malacca, Malaysia, May 2012, pp. 199–204.
    19. S. Panth, K. Samadi, Y. Du, and S.-K. Lim, “Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs,” in Proc. ISPD, Petaluma, CA, USA, Jan. 2014, pp. 47–54.

Recent Article