Author : Akshata Mathad 1
Date of Publication :24th May 2018
Abstract: Major Component which decides the performance of the digital circuit is Clock, which is a multi-fanout signal. If the clock frequency is high, so the performance. In this paper techniques to reduce clock network length are discussed. Clock nets are first migrated from higher technology node to lower technology node and then modified to achieve less dynamic capacitance by reducing the length of clock net. Here, clock network of Full Chip is studied and identified the corner cases by using a Perimeter as an objective function where clock network could be optimized. Minimum Length Routing is done using Intel Custom Tools, which ultimately reduced the capacitance of the clock network. Clock network is optimized using two techniques; 1. Trunk router and 2. Netcell Estimation router. Experimental results show that 20.91% and 6.01% reduction in clock net length by using Trunk and Netcell Estimation routers respectively
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