Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

A Proficient DLAU Design for FPGA Implementation

Author : Vijayashree 1

Date of Publication :25th May 2018

Abstract: These days, the size of systems are increasingly large scale due to the practical applications, which poses significance importance in the field of neural networks. Deep neural networks(DNN)has been employed for image recognition since it can accomplish high exactness by copying conduct of optic nerve in living animal. In order to enhance the execution and additionally to keep up low power cost, in this paper, we design deep learning accelerator unit(DLAU), which is the scalable accelerator for largescale networks using field-programmable gate array(FPGA) as hardware prototype. In order to improve throughput, it utilizes the tile techniques and employs three pipelined processing units to explore the locality for deep learning applications

Reference :

    1. Chao Wang,Li Gong,Qi yu,Xi Li, “A Scalable Deep Learning Accelerator Unit on FPGA”, vol.36, No.3,2017.
    2. D.L.Ly and P.Chow,”A high-performance FPGA architecture for restricted Boltzmann machines”, in proc. FPGA, Montery, CA, USA, 2009, pp,73-82.
    3. C.Zhang et al.,”optimizing FPGA-based accelerator design for deep convolution neural networks”, in proc. FPGA, Monterey, CA, USA, 2015
    4. Q.Yu, C.Wang,X.Ma, X.Li, and X. Zhou, “A Deep Learning Prediction process accelerator based FPGA”, in proc. CCGRID, Shenzhen, china, 2015, pp.1159-1162.
    5. T. chen et al., “DianNao: A small-footprint highthroughput accelerator for obiquitous machine –learning,” in proc.ASPLOS,salt Lake city, UT,USA,2014,pp.269-284
    6. S.K.Kim,L.C. McAee, P.L. McMahon, and K. Olukotun, “A highly scalable restricted Boltzmann Machine FPGA implementation”, in proc. FPL,prague,Czech Republic,2009,pp.367-372
    7. J.Qu et al., “Going deeper with embedded FPGA platform for convolution neural network”, in proc. FPGS, Montery, CA,USA, 2016, pp.26-35.
    8. P. Thinbodeau. Data centers are the New polluters. Accessed on Apr. 4, 2016.[online]. Available: http://www.computerworld.com/ article/2598562/datacenter/data-centers-the-new-polluters.html
    9. J. Hauswald et al., “DjiNN and Tonic: DNN as a service and its implictions for future warehouse scale computers.” In proc. ISCA, Portland. OR. USA, 2015, pp,27-40
    10. P. Ferreira, P. Ribera, A. Attunes, and F. M. Dias, “A high bit resolution FPGA implementation of FNN with a new algorithm for activation of FNN with a new algorithm for the activation function”, Neurocomputing, vol.71,pp.71- 77,2007.
    11. K. Simonyan and A. Zisserman, “very deep convolutional networks for large-scale image recognition,” arXiv preprint arXiv:1408.1556,2014.
    12. D. Liu, T. Chen, S. Liu, J. Zhou, S. Zhou, O. Teman, X. Feng, X. Zhou, and Y. Chen, “pudiannao: A polyvalent machine learning accelerator,” in ASPLOS ACM, 2015, pp 369- 381.
    13. M. A. Erdogdu, “Newton-stein method: A second order method for g1ms via steins lemma”, in advances in neural Information processing systems 28, 2015, pp. 1216-1224..

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