Author : Akshata A. Udpikar 1
Date of Publication :21st June 2018
Abstract: In the recent years, radio frequency identification has come a long way from anonymity into mainstream applications that help speed up the access control, authentication, ski ticketing etc. As a finely-honed version of high-frequency Radio Frequency Identification, Near Field Communication devices, have taken benefits of the shorter read range boundaries of its radio frequency i.e. 13.56MHz. NFC facilitates short-range exchange between attuned devices; which implies that they only operate when the two devices are brought closer to each other or they touch. One of the devices must be powered on for a two-way exchange to take place. The second device saves its battery for other things, or it may not have a battery at all. This paper is based on building a Universal Verification Methodology Verification Component based on ISO/IEC 15693 protocol i.e. Type 5 NFC tags. The methodology used to build the verification component was Universal Verification Methodology. This UVM Verification Component developed can be reused in any application of NFC tag which is based on the ISO/IEC 15693 protocol with little modifications to the test bench architecture.
Reference :
-
- Vedat Coskun, Busra Ozdenizci, Kerem OkA,” Survey on Near Field Communication (NFC)”, Technology, Springer Science+Business Media New York, December2012
- Busra OZDENIZCI, Kerem OK, Vedat COSKUN, Mehmet N. AYDIN, “Development of an Indoor Navigation System Using NFC Technology”, Fourth International Conference on Information and Computing IEEE, 2011.
- Ruhanen, M. Hanhikorpi et al, “Sensor Enabled Tag Handbook”, 2008.
- James C. Chen, Po Tsang B. Huang, Chien-Jung Huang, “Warehouse management with lean and RFID application: a case study, Int. J. Adv. Manuf. Technology”., Vol. 69, 2013, pp. 531-542.
- Identification Cards-Contactless integrated circuit cards-Vicinity cards, IS0/IEC, 2006.
- Young-Nam Yun; “Beyond UVM for practical SoC verification”, SoC Design Conference (IS0CC), 2011 International, pp158-162, 2011.
- Juan Franscesconi, J. Agustin Rodriguez, Pedro. M. Julian, “UVM Based Testbench Architecture for Unit Verification”, Argentine School of Micro-Nanoelectronics, Technology and Applications, 2014. ISBN: 978-987-1907- 86-1.
- Janick Bergeron, “Writing testbenches – Functional Verification of HDL models”, Pearson, Second Edition, 2003.
- Hung-Yi Yang, “Highly Automated and Efficient Simulation Environment with UVM”, .VLSI-DAT, 2014.
- Pranay Samanta, Deepak Chauhan, Sujay Deb, Piyush Kumar Gupta, “UVM based STBUS Verification IP for verifying SoC Architectures”, ISBN: 978-1-4799-4006- 6/14, IEEE 2014.