Author : Shwetha 1
Date of Publication :21st June 2018
Abstract: In contemporary era of technology, minimizing power consumption during functional as well as during testing has become one of the crucial requirements for semiconductor industries. Design-ḟor-Testability (DFT) and low-power issues are greatly associated with each other. The trouble of test power reduction could be addressed at different stages of test-generation for logic designs. Switching activity reduction is the main area to concentrate on during low power testing. This paper provides comprehensive analysis on various novel low-power ATPG and DFT techniques such as Q-gating, EDT, X-filling techniques etc. Shift/Capture power as well as switching activities are calculated for these approaches on logic designs. By means of PowerArtist, a power analysis tool, power numbers are captured for these techniques and comparative analysis of results are made to find optimal techniques which could meet design specifications with not much loss of test and fault coverage. This paper reports on DFT methods which can aid for achieving comprehensive low power through commercial DFT tools in testing phase of VLSI design cycle.
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