Open Access Journal

ISSN : 2394-6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Design Of Shift Register Using Current Mode Logic D Flip Flops

Author : Jaya Sri Lakshmi V 1 Sagar Krishna S 2

Date of Publication :10th June 2020

Abstract: Over past few years, the surpassing advancements in Integrated system technologies is; there is a major solid growth in using micro circuitry devices. In this digital world, electronic devices like computers, mostly use registers for multi purposes. Theme of the paper is to Design a Shift Register using CML technique D-Flip Flops. This idea is used for low voltage supply and speed improvement. D flip-flop is designed using D-latches. To satisfy the speed requirements, D-latches are usually designed in current-mode logic (CML). The CML is itself a MOS differential pair. In this paper, D latches are designed using conventional method, triple-tail method, folded method and their performance is compared in terms of Power (Reference Current ISS over 500μ A) and delay. The folded D latch gives best results in terms performance and delay. This folded D latch is used for the design of d flip-flops. With the help of D Flip-Flops, the proposed Shift Register is implemented.

Reference :

  1. 1. P. Payandehnia, H. Maghami, S. Sheikhaei, et al, “High speed CML latch using active inductor in 0.18μm CMOS technology,” Iranian Conference on Electrical Engineering, Tehran. Iran, pp. 1-4, May 2011,.

    2. M. Usama and T. Kwasniewski, “New CML latch structure for high speed pre-scaler design,” Canadian Conference on Electrical and Computer Engineering, vol. 4, , pp. 1915- 1918 May 2004.

    3. P. Heydari and R. Mohavavelu, “Design of ultra-high-speed CMOS CML buffers and latches,” International Symposium on Circuits and Systems, vol. 2, , pp. 208-211, May 2003.

    4. M. H. Anis and M. I. Elmasry, “Self-timed MOS current mode logic for digital applications,” in Proc. IEEE Int. Conf. ASIC/SOC, pp. 193–197, 2002.

    5. B. Razavi, Design of Analog CMOS Integrated Circuits. New

    6. York: McGraw-Hill, pp. 101–134, 2001.

    7. Vladimir Stojanovic, and Vojin G. Oklobdzija, “Comparative Analysis of Master-Slave Latches and Flip- Flops for High-Performance and Low-Power Systems,” IEEE JSSC, Vol. 34, No. 4, April 1999.

    8. C. Yang, G. Dehng, J. Hsu, S. Liu, "New Dynamic Flip-Flops for High-speed DualModulus Pre-scaler," IEEE Jour. of Solid-state Circ., vol. 33, no. 10, pp. 1568-1571, Oct. 1998.

    9. B. Razavi, Y. Ota, R. Swartz, "Design techniques for low-voltage high speed digital bipolar circuits," IEEE Jour. of Solid-state Circ., Vol. 29, No. 2, pp. 332-339, March 1994.

    10. K. Kishine, Y. Kobayashi, H. Ichino, "A High-speed, Low-Power Bipolar Digital Circuit for Gb/s LSI's: Current Mirror Control Logic," IEEE Jour. of Solid-state Circ., Vol. 32, No. 2, pp. 215-221, February 1997.

    11. M. Alioto - G. Palumbo, "Modelling and optimized design of current mode MUX/XOR and D Flip-Flop,” IEEE Trans. on CASpart I I , V. 47, No.5, pp.452-461, May,'00.

    12. S. A. Tajalli, E. Vittoz, E. J. Braurer, Y. Leblebici, "Ultra-low power sub threshold current- mode logic utilizing PMOS load device“ Electronics Letters, vol. 43, no. 17, August 2007

    13. Heydari, P., Mohavavelu, R., ”Design of Ultra High- Speed CMOS CML buffers and Latches, ” Proceeds' of the 2003 ISCAS, Vol. 2, May 2003.

    14. Phillip Chin, Junjie Su, and Xiaolan Zhong, “ Analysis and Design ofHigh Performance and Low Power Current Mode Logic CMOS”,University of California, Berkeley.

    15. J. Ramírez-Angulo, R. G. Carvajal, and A. Torralba, “Low SupplyVoltage HighPerformance CMOS Current Mirror With Low Input andOutput Voltage Requirements”, IEEE Transactions on Circuits and Systems, vol. 51, no. 3, pp. 124–129, March 2004.

    16. Massimo Alioto, Rosario Mita and Gaetano Palumbo, “ Performance Evaluation of the Low-Voltage CML D-latch topology,” Integration,VLSI Journal, vol. 36, no. 4, pp. 191-209, 2003.

    17. I. Jang, Y. Lee, S. Kim, and J. Kim, “Powerperformance tradeoff analysis of CML-based high-speed transmitter designs using circuitlevel optimization,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 63, no. 4, pp. 540–550, Apr. 2016.

    18. M. Alioto and G. Palumbo, Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits. New York, NY, USA: Springer, 2015.

    19. M. Alioto, R. Mita, and G. Palumbo, “Performance evaluation of the low-voltage CML D-latch topology,” Integr., VLSI J., vol. 36, no. 4, pp. 191–209, 2003.

    20. N. Pandey, K. Gupta, G. Bhatia, and B. Choudhary, “MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells,” Microelectron. J., vol. 57, no. 11, pp. 13–20, Nov. 2016.

    21. J. Ramirez-Angulo, R. G. Carvajal, and A. Torralba, “Low supply voltage highperformance CMOS current mirror with low input and output voltage requirements,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 51, no. 3, pp. 124–129, Mar. 2004.


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DOI : 10.36647/ijerece/0000