Author : Dharani B 1
Date of Publication :13th May 2020
Abstract: Increased usage of battery-operated compact devices such as notebooks, Smart phones, e-readers, MP3 players and many other devices are designed with built-in storage, smaller silicon area, longer battery life, higher speed and more reliability. Full adder is being dominant block in arithmetic operations. The main block of the full adder circuit is the XOR/XNOR gate, as the XOR/XNOR gate consumes more power. The power consumed by the full adder is therefore reduced by optimizing the design of the XOR / XNOR gates. These can be used in a variety of multipliers, such as Vedic, Wallace, Array, etc. Simulation results are performed in Cadence Virtuoso tool 45-nm CMOS technology with 0.45V supply voltage. The novel structures of XOR / XNOR gate are proposed for the design of hybrid full adders with low power, high speed and less PDP. The proposed HFA-14T has superior speed against other full adder cells with less number of transistors. Therefore, Area of the proposed HFA’s is also reduced.
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